In recent years, a structured array device has drawn attention, which enables a purchaser to customize an interconnect layer of the device to realize a system on chip (SoC) device. A base array structure of the structured array device is typically formed by diverting a base array structure of a field-programmable gate array (FPGA). However, the structured array device in this case has problems that a degree of integration of the device is low and timing convergence of the device is deteriorated, which results in enlargement of the chip size of the device and degradation of the performance of the device.